Integrating different devices, such as the memory cell and the logic circuit on the same wafer has become a trend in the semiconductor industry. This has provided portable electronic devices such as digital cameras, notebooks, personal digital assistants (PDA), mobile phones, and the like. All of these devices need a dependable and convenient method to maintain their information and/or data for substantial periods of time without refresh cycles and/or power—non-volatile memory. A widely utilized type of non-volatile memory device is flash memory. Flash memory devices achieve relatively high speeds of operation and are able to maintain their data without power and/or refresh cycles.
A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM. Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of programming and/or erasing multiple memory cells at once, hence the term flash EEPROM.
The specific structure of flash memory cells can be varied and include, for example, those described in U.S. Pat. Nos. 6,667,201; 6,281,089; 6,720,217; and 6,265,267. The components of the memory cells, and the memory cells in an array are isolated from each other, typically by the use of shallow trench isolation structures (STI). Methods of forming STI structures in a semiconductor substrate are well known in the art and include, for example, those described in U.S. Pat. Nos. 6,239,002; 5,933,749; and 6,784,077.
Flash memory devices are programmed and erased by pulses that place charges in selected memory cells or drain charges away. Additionally, blocks and arrays of memory cells can be erased at a single time by an erase operation such as a channel erase. For example, U.S. Pat. Nos. 6,552,360; 6,593,606; 5,889,698; 6,191,980; and 6,125,059 describe programming of these type devices.
Erase operations for flash memory devices are typically performed at greater voltage levels than those used in standard non-flash memory devices. Such erase operations can cause operation of flash memory devices and the devices themselves to be susceptible to extrinsic defects, introduced in the fabrication process. Costly and time intensive testing can be performed to identify devices with extrinsic defects, such as that described in U.S. Pat. No. 6,717,850. Although the defective memory cells can be identified by this testing, the extrinsic defects are not necessarily identified. An understanding of the specific defect and an improved fabrication process that eliminates the extrinsic defect(s) are desired.